CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 585

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The receive cases are more complicated.
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
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Start of Bit Time
Start of Bit Time
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
Transmit 1
Transmit 0
Perceived
Perceived
Speedup
Drive to
Pulse
Host
Host
Host
Synchronization
Uncertainty
Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Figure 15-8. BDM Host-to-Target Serial Bit Timing
MC9S12XDP512 Data Sheet, Rev. 2.21
10 Cycles
R-C Rise
Figure 15-9
10 Cycles
10 Cycles
Target Senses Bit
shows the host receiving a logic 1 from the target
Host Samples
High-Impedance
Chapter 15 Background Debug Module (S12XBDMV2)
BKGD Pin
High-Impedance
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of
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