CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 551

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4
Figure 13-19
control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger
interface.
13.4.1
As shown in
16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with
two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer
is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX)
register.
A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer
(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register
is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro
time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter
will load its start value as specified in the PITMTLD0 or PITMTLD1 register and will start down-counting.
Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the
connected 16-bit modulus down-counters count one cycle.
Freescale Semiconductor
Bus
Clock
Functional Description
PFLMT
[0]
[1]
Timer
Figure
shows a detailed block diagram of the PIT module. The main parts of the PIT are status,
PITCFLMT Register
PITFLT Register
PITMUX Register
PITMLD0 Register
8-Bit Micro Timer 0
PITMLD1 Register
8-Bit Micro Timer 1
13-1and
Figure
PMUX3
Figure 13-19. PIT Detailed Block Diagram
4
4
MC9S12XDP512 Data Sheet, Rev. 2.21
13-19, the 24-bit timers are built in a two-stage architecture with four
PMUX0
PFLT0
PFLT2
PFLT1
PFLT3
[1]
[2]
Timer 0
Timer 1
Timer 2
Timer 3
PITLD0 Register
PITCNT0 Register
PITLD1 Register
PITCNT1 Register
PITLD2 Register
PITCNT2 Register
PITLD3 Register
PITCNT3 Register
Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
Time-Out 3
time-
out 1
time-
out 2
time-out 0
PIT_24B4C
PITTF Register
PITINTE Register
Interrupt /
Trigger Interface
Hardware
Trigger
Interrupt
Request
4
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