CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 702

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module

Read: Anytime

Write: Never

Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer.

When the CNT rolls over to 0, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger

or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1. The DBGCNT

occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer

entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace

This applies to normal/loop1 modes when tracing from either CPU or XGATE only.

Debug Count Register (DBGCNT)

Unimplemented or Reserved

shows the correlation between the CNT bits and the number of valid data lines in the trace buffer.

Figure 19-9. Debug Count Register (DBGCNT)

Table 19-17. DBGCNT Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Table 19-18. CNT Decoding Table

oldest data has been overwritten by most recent data

ARM bit will be cleared and the tracing session ends.

64 lines valid; if using begin-trigger alignment,

32 bits of one line valid

1.5 lines valid

64 lines valid,

No data valid

62 lines valid

63 lines valid

2 lines valid

3 lines valid

1 line valid

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