CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 885

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.4.3
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
22-69).
Pin Interrupts
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1
Figure 22-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
These values include the spread of the oscillator frequency over temperature,
voltage and process.
Uncertain
Ignored
Pulse
Valid
t
Table 22-69. Pulse Detection Criteria
pign
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 22-78. Pulse Illustration
3 < t
t
pval
t
t
pulse
pulse
STOP
pulse
(Figure
< 4
3
4
uncertain
t
22-78) shorter than a specified time from generating an
pulse
Bus clocks
Bus clocks
Bus clocks
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Unit
Mode
t
pign
t
t
pulse
pulse
< t
STOP
pulse
t
t
pign
pval
1
< t
pval
(Figure 22-77
and
887