CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1032

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by
4 consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is
generated by an RC-oscillator in the port integration module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).
24.0.9
24.0.9.1
No low-power options exist for this module in run mode.
1034
Low-Power Options
Run Mode
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
Figure 24-69. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Uncertain
1. These values include the spread of the oscillator frequency over
Ignored
Pulse
Valid
temperature, voltage and process.
t
Table 24-62. Pulse Detection Criteria
pign
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 24-70. Pulse Illustration
3 < t
t
pval
t
t
pulse
pulse
STOP
pulse
< 4
3
4
uncertain
t
pulse
Bus clocks
Bus clocks
Bus clocks
Unit
Mode
t
pign
t
t
pulse
pulse
< t
STOP
pulse
t
t
pign
pval
1
< t
pval
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