CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1029

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the

BKGD pin is used as MODC input.

Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O.

Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.

Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2

output running at the core clock rate. The clock output is always enabled in emulation modes.

Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK

output running at the bus clock rate or at the programmed divided clock rate. The clock output is

always enabled in emulation modes.

Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-

sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit

(Section 24.0.5.10, “IRQ Control Register

code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-

Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ

interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It

is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.

Port K pins PK[7:0] can be used for either general-purpose I/O.

Port A and B

Table 24-61. Module Implementations on Derivatives

MSCAN Modules

(IRQCR)”) and clearing the I-bit in the CPU’s condition