CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 412

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it.If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

This is the basic mode of operation.

IIC operation in wait mode can be conﬁgured. Depending on the state of internal bits, the IIC can operate

normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module

enters a power conservation state during wait mode. In the later case, any transmission or reception in

progress stops at wait mode entry.

The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC

Operation in Run Mode

Operation in Wait Mode

Operation in Stop Mode

Clock Stretching

Internal Counter Reset

Figure 9-11. IIC-Bus Clock Synchronization

MC9S12XDP512 Data Sheet, Rev. 2.21

Start Counting High Period

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