CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 80

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.1.2
This subsection lists and briefly describes all operating modes supported by the CRG.
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Run mode
All functional parts of the CRG are running during normal run mode. If RTI or COP functionality
is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to
be set to a nonzero value.
Wait mode
In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL
register.
Stop mode
Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode
(PSTP = 0) and pseudo stop mode (PSTP = 1).
— Full stop mode
— Pseudo stop mode
Self clock mode
Self clock mode will be entered if the clock monitor enable bit (CME) and the self clock mode
enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as self clock mode is entered, the CRG starts to perform a clock quality check. Self
clock mode remains active until the clock quality check indicates that the required quality of the
incoming clock signal is met (frequency and amplitude). Self clock mode should be used for safety
purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing
severe system conditions.
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set, the COP and RTI will continue to run, or else they remain frozen.
Modes of Operation
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor