CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 57

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.3.10
PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
1.2.3.11
PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
1.2.3.12
PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for
the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation,
this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
1.2.3.13
PB[7:0] are general-purpose input or output pins.
1.2.3.14
PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are
configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds
for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.15
PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an
external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for
PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage
thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.16
PE7 is a general-purpose input or output pin. The XCLKS is an input signal which controls whether a
crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether
full swing Pierce oscillator/external clock circuitry is used.
Freescale Semiconductor
PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0
PB[7:0] — Port B I/O Pins
PC[7:0] / DATA [15:8] — Port C I/O Pins
PD[7:0] / DATA [7:0] — Port D I/O Pins
PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7
MC9S12XDP512 Data Sheet, Rev. 2.21
Chapter 1 Device Overview MC9S12XD-Family
57