CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 326

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.10
Read or write: Anytime
All bits reset to zero.
The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register.
326
Reset
C[7:0]I
Field
7:0
W
R
Input Capture/Output Compare “x” Interrupt Enable
0 The corresponding flag is disabled from causing a hardware interrupt.
1 The corresponding flag is enabled to cause an interrupt.
C7I
Timer Interrupt Enable Register (TIE)
0
7
C6I
0
6
Figure 7-15. Timer Interrupt Enable Register (TIE)
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 7-13. TIE Field Descriptions
C5I
0
5
C4I
0
4
Description
C3I
0
3
C2I
0
2
Freescale Semiconductor
C1I
0
1
C0I
0
0

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