CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 103

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.1.5
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus a system reset is initiated (see
Watchdog
allow selection of seven COP time-out periods.
When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register
during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program
fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is
written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in pseudo stop mode.
2.4.1.6
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK. At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period
starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in pseudo stop mode.
2.4.2
2.4.2.1
The CRG block behaves as described within this specification in all normal modes.
1. A Clock Monitor Reset will always set the SCME bit to logical 1.
Freescale Semiconductor
(COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register
Operating Modes
Computer Operating Properly Watchdog (COP)
Real Time Interrupt (RTI)
Normal Mode
Remember that in parallel to additional actions caused by self clock mode
or clock monitor reset
check the OSCCLK signal.
The clock quality checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f
during pseudo stop mode or wait mode.
MC9S12XDP512 Data Sheet, Rev. 2.21
1
handling the clock quality checker continues to
NOTE
Section 2.4.1.5, “Computer Operating Properly
SCM
Chapter 2 Clocks and Reset Generator (S12CRGV6)
) and an active VREG
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