CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 442

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
442
Module Base + 0x0018 (CANIDAR4)
AC[7:0]
Field
7:0
Figure 10-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
Table 10-20. CANIDAR0–CANIDAR3 Register Field Descriptions
AC6
AC6
AC6
AC6
0
0
0
0
6
6
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
AC4
AC4
AC4
AC4
Description
0
0
0
0
4
4
4
4
AC3
AC3
AC3
AC3
3
0
3
0
3
0
3
0
AC2
AC2
AC2
AC2
0
0
0
0
2
2
2
2
Freescale Semiconductor
AC1
AC1
AC1
AC1
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0