CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 337

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.19
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
MCPR[1:0]
MODMC
RDMCL
Reset
MCEN
ICLAT
FLMC
Field
MCZI
1:0
7
6
5
4
3
2
W
R
MCZI
Modulus Counter Underflow Interrupt Enable
0 Modulus counter interrupt is disabled.
1 Modulus counter interrupt is enabled.
Modulus Mode Enable
0 The modulus counter counts down from the value written to it and will stop at 0x0000.
1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
Read Modulus Down-Counter Load
0 Reads of the modulus count register (MCCNT) will return the present value of the count register.
1 Reads of the modulus count register (MCCNT) will return the contents of the load register.
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3
and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will always return zero.
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets
the modulus counter prescaler.
Write zero to this bit has no effect. Read of this bit will return always zero.
Modulus Down-Counter Enable
0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early
1 Modulus counter is enabled.
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler
when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of
the load register into the modulus counter count register occurs.
16-Bit Modulus Down-Counter Control Register (MCCTL)
0
7
value written to the modulus count register.
interrupt flag when the modulus down-counter is enabled.
the modulus counter to 0xFFFF.
Figure 7-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)
MODMC
0
6
Table 7-22. MCCTL Field Descriptions
RDMCL
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
ICLAT
0
0
4
Description
FLMC
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
3
MCEN
0
2
MCPR1
0
1
MCPR0
0
0
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