CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 662

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 18 Memory Mapping Control (S12XMMCV3)

Read: Anytime

Write: anytime in special modes, one time only in other modes.

This register determines the position of the 256 Byte direct page within the memory map.It is valid for both

global and local mapping scheme.

Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global

instruction in direct addressing mode or by the appropriate local address to the global address expansion

Address: 0x0011

Section 18.4.2.1.1, “Expansion of the Local Address

Example 18-2. This example demonstrates usage of the Direct Addressing Mode

Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct

addressing mode. The bits from this register form bits [15:8] of the address (see

Direct Page Register (DIRECT)

XGATE write access to this register during an CPU access which makes use

of this register could lead to unexpected results.

#0x80,DIRECT

Figure 18-9. DIRECT Address Mapping

Table 18-9. DIRECT Field Descriptions

Figure 18-8. Direct Register (DIRECT)

MC9S12XDP512 Data Sheet, Rev. 2.21

Global Address [22:0]

;Set DIRECT register to 0x80. Write once only.

;Global data accesses to the range 0xXX_80XX can be direct.

;Logical data accesses to the range 0x80XX are direct.

;Load the Y index register from 0x8000 (direct access).

;< operator forces direct access on some assemblers but in

;many cases assemblers are “direct page aware” and can

CPU Address [15:0]

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