CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 831

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

22.3.2.10 Port E Data Direction Register (DDRE)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Freescale Semiconductor

Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general

purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be conﬁgured as outputs. Port E, bits

1 and 0, can be read regardless of whether the alternate interrupt function is enabled.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTE after changing the DDRE register.

= Unimplemented or Reserved

Figure 22-12. Port E Data Direction Register (DDRE)

Table 22-13. DDRE Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)