CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 358

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.4.1.1.3
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is
explained in the diagram and notes below.
In
358
Figure 7-72
2. IC Queue Mode (LATQ = 0)
1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.
2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
4. Input pulses with a duration of DLY_CNT or longer are accepted.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
This will prevent the captured value from being overwritten until it is read or latched in the holding
register.
The main timer value is memorized in the IC register by a valid input pin transition (see
and
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the value of the IC register will be transferred to its holding register and the IC register
memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
In queue mode, reads of the holding register will latch the corresponding pulse accumulator value
to its holding register.
accepted, depending on their relative alignment with the sample points.
accepted, depending on their relative alignment with the sample points.
Figure
BUS CLOCK
Delayed IC Channels
a delay counter value of 256 bus cycles is considered.
INPUT ON
INPUT ON
INPUT ON
INPUT ON
DLY_CNT
CH0–3
CH0–3
CH0–3
CH0–3
7-68).
Figure 7-72. Channel Input Validity with Delay Counter Feature
0
MC9S12XDP512 Data Sheet, Rev. 2.21
1
2
255.5 Cycles
255.5 Cycles
255 Cycles
256 Cycles
3
253
254
255
Section 7.4.1.1, “IC
Section 7.4.1.1, “IC
256
Accepted
Rejected
Accepted
Rejected
Freescale Semiconductor
Channels”).
Figure 7-67
Channels”).