CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 274

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 XGATE (S12XGATEV2)
SBC
Operation
RS1 - RS2 - C
Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using
binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward
from the previous operation allowing 32 and more bit subtractions.
Example:
CCR Effects
Code and CPU Cycles
274
N:
Z:
V:
C:
SBC RD, RS1, RS2
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Z
SUB
SBC
BCC
V
Source Form
C
RD
R6,R4,R2
R7,R5,R3
new
| RS1[15] & RS2[15] & RD[15]
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
TRI
; R7:R6 = R5:R4 - R3:R2
; conditional branch on 32 bit subtraction
new
Subtract with Carry
| RS2[15] & RD[15]
0
0
0
1
1
new
new
Machine Code
RD
RS1
RS2
Freescale Semiconductor
SBC
0
1
Cycles
P