CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 82

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.2
This section lists and describes the signals that connect off chip.
2.2.1
These pins provide operating voltage (V
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, V
and V
2.2.2
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
that eliminates the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device specification for
calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied
to V
2.2.3
RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a
known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has
been triggered.
2.3
This section provides a detailed description of all registers accessible in the CRG.
82
DDPLL
SSPLL
External Signal Description
Memory Map and Register Definition
.
V
XFC — External Loop Filter Pin
RESET — Reset Pin
must be connected to properly.
DDPLL
and V
SSPLL
Figure 2-2. PLL Loop Filter Connections
MC9S12XDP512 Data Sheet, Rev. 2.21
MCU
— Operating and Ground Voltage Pins
DDPLL
XFC
) and ground (V
R
C
S
S
SSPLL
C
P
V
DDPLL
) for the PLL circuitry. This allows
Freescale Semiconductor
DDPLL