CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 864

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.53 Port H Interrupt Flag Register (PIFH)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSH register. To clear this flag, write logic level “1” to the corresponding bit in the
PIFH register. Writing a “0” has no effect.
866
PIFH[7:0]
Reset
Field
7–0
W
R
PIFH7
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
7
Writing a logic level “1” clears the associated flag.
PIFH6
0
6
Figure 22-55. Port H Interrupt Flag Register (PIFH)
Table 22-50. PIFH Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PIFH5
0
5
PIFH4
0
4
Description
PIFH3
0
3
PIFH2
0
2
Freescale Semiconductor
PIFH1
0
1
PIFH0
0
0

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