CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 114

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
114
Sampled RESET Pin
after release)
(64 cycles
1
1
1
0
SYSCLK
RESET
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
Reset Pending
Clock Monitor
X
0
1
0
Possibly
SYSCLK
not
running
Table 2-15. Reset Vector Selection
MC9S12XDP512 Data Sheet, Rev. 2.21
CRG drives RESET pin low
) (
Figure 2-25. RESET Timing
Reset Pending
COP
With n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
X
X
0
1
128 + n cycles
NOTE
) (
)
(
POR / LVR / Illegal Address Reset / External Reset
POR / LVR / Illegal Address Reset / External Reset
RESET pin
released
64 cycles
)
(
with rise of RESET pin
Clock Monitor Reset
Vector Fetch
Possibly
RESET
driven low
externally
COP Reset
)
(
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