CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 312

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3
This section provides a detailed description of all memory and registers.
7.3.1
The memory map for the ECT module is given below in
the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
312
Memory Map and Register Definition
Address
0x000C
0x000D
0x001C
0x001D
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x001A
0x001B
Offset
Module Memory Map
Timer Input Capture/Output Compare Select (TIOS)
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
Output Compare 7 Data Register (OC7D)
Timer Count Register High (TCNT)
Timer Count Register Low (TCNT)
Timer System Control Register 1 (TSCR1)
Timer Toggle Overflow Register (TTOV)
Timer Control Register 1 (TCTL1)
Timer Control Register 2 (TCTL2)
Timer Control Register 3 (TCTL3)
Timer Control Register 4 (TCTL4)
Timer Interrupt Enable Register (TIE)
Timer System Control Register 2 (TSCR2)
Main Timer Interrupt Flag 1 (TFLG1)
Main Timer Interrupt Flag 2 (TFLG2)
Timer Input Capture/Output Compare Register 0 High (TC0)
Timer Input Capture/Output Compare Register 0 Low (TC0)
Timer Input Capture/Output Compare Register 1 High (TC1)
Timer Input Capture/Output Compare Register 1 Low (TC1)
Timer Input Capture/Output Compare Register 2 High (TC2)
Timer Input Capture/Output Compare Register 2 Low (TC2)
Timer Input Capture/Output Compare Register 3 High (TC3)
Timer Input Capture/Output Compare Register 3 Low (TC3)
Timer Input Capture/Output Compare Register 4 High (TC4)
Timer Input Capture/Output Compare Register 4 Low (TC4)
Timer Input Capture/Output Compare Register 5 High (TC5)
Timer Input Capture/Output Compare Register 5 Low (TC5)
Timer Input Capture/Output Compare Register 6 High (TC6)
Timer Input Capture/Output Compare Register 6 Low (TC6)
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 7-1. ECT Memory Map
Register
Table
7-1. The address listed for each register is
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3