CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 843
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.3.2.25 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin
is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive
channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
Freescale Semiconductor
DDRS[7:0]
Reset
Field
7–0
W
R
DDRS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTS or PTIS registers, when changing the DDRS register.
DDRS6
0
6
Figure 22-27. Port S Data Direction Register (DDRS)
Table 22-27. DDRS Field Descriptions
DDRS5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRS4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRS3
0
3
DDRS2
0
2
DDRS1
0
1
DDRS0
0
0
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