CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1126

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
1128
TRY TO DECREASE Tbus
Figure 27-24. Determination Procedure for PRDIV8 and FDIV Bits
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ s])-1
yes
ALL COMMANDS IMPOSSIBLE
FCLK=(PRDCLK)/(1+FDIV[5:0])
PRDCLK[MHz]*(5+Tbus[ s])
1/FCLK[MHz] + Tbus[ s] > 5
PRDCLK=oscillator_clock/8
MC9S12XDP512 Data Sheet, Rev. 2.21
PRDIV8=0 (reset)
FCLK > 0.15MHz
oscillator_clock
FDIV[5:0] > 4?
Tbus < 1 s?
an integer?
PRDIV8=1
START
12.8MHz?
AND
?
yes
yes
yes
no
no
no
no
PRDCLK=oscillator_clock
no
yes
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ s]))
ALL COMMANDS IMPOSSIBLE
END
Freescale Semiconductor

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