CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 496

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 11 Serial Communication Interface (S12SCIV5)

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the

transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.

The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is

synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the

transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to one source of error:

When IREN = 0 then,

Integer division of the bus clock may not give the exact target frequency.

SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

Baud Rate Generation

lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.

Table 11-15. Baud Rates (Example: Bus Clock = 25 MHz)

The address bit identiﬁes the frame as an address

character. See

MC9S12XDP512 Data Sheet, Rev. 2.21

Section 11.4.6.6, “Receiver

Freescale Semiconductor