CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 802

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.5.2.1
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 21-5
The timing diagram for this operation is shown in:
The associated timing numbers are given in:
Timing considerations:
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Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAITE = 0)’
Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
LSTRB has the same timing as R/W.
ECLKX2 rising edges have the same timing as ECLK edges.
The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
shows the PRU connection with the available external bus signals in an emulator application.
Example 2a: Emulation Single-Chip Mode
Figure 21-5. Application in Emulation Single-Chip Mode
ADDR[22:20]/ACC[2:0]
ADDR[22:0]/IVD[15:0]
S12X_EBI
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
MC9S12XDP512 Data Sheet, Rev. 2.21
ECLKX2
LSTRB
ECLK
R/W
EMULMEM
PRU
Emulator
PRR
Ports
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