CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 446

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Figure 10-24

identiﬁers. The mapping of standard identiﬁers into the IDR registers is shown in

All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation

All reserved or unused bits of the receive and transmit buffers always read ‘x’.

1. Exception: The transmit priority registers are 0 out of reset.

Not applicable for receive buffers

Read-only for CPU

shows the common 13-byte data structure of receive and transmit buffers for extended

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor