CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1086

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
1088
TRY TO DECREASE Tbus
Figure 26-17. Determination Procedure for PRDIV8 and EDIV Bits
EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ s])–1
EECLK = (PRDCLK)/(1+EDIV[5:0])
ALL COMMANDS IMPOSSIBLE
yes
1/EECLK[MHz] + Tbus[ms] > 5
PRDCLK = oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[ s])
MC9S12XDP512 Data Sheet, Rev. 2.21
EECLK > 0.15 MHz
PRDIV8 = 0 (reset)
oscillator_clock
EDIV[5:0] > 4?
Tbus < 1 s?
>12.8 MHz?
PRDIV8 = 1
an integer?
START
AND
?
yes
yes
yes
no
no
no
no
PRDCLK = oscillator_clock
no
EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ s]))
yes
ALL COMMANDS IMPOSSIBLE
END
Freescale Semiconductor

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