CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1085

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the

optimum target by:

If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the

ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written

to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR

ﬂag in the ESTAT register will set.

Freescale Semiconductor

Program and erase command execution time will increase proportionally

with the period of EECLK. Because of the impact of clock synchronization

on the accuracy of the functional timings, programming or erasing the

EEPROM memory cannot be performed if the bus clock runs at less than 1

MHz. Programming or erasing the EEPROM memory with EECLK < 150

kHz should be avoided. Setting ECLKDIV to a value such that EECLK <

150 kHz can destroy the EEPROM memory due to overstress. Setting

ECLKDIV to a value such that (1/EECLK+Tbus) < 5 s can result in

incomplete programming or erasure of the EEPROM memory cells.

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)