CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 556

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.1.3
Figure 14-1
REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
556
V
V
V
DDR
DDA
SSA
Bus Clock
Block Diagram
shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
V
REGEN
LVD
LVD: Low-Voltage Detect
LVR: Low-Voltage Reset
POR: Power-On Reset
Figure 14-1. VREG_3V3 Block Diagram
CTRL
MC9S12XDP512 Data Sheet, Rev. 2.21
API
Rate
Select
REG2
REG1
REG: Regulator Core
CTRL: Regulator Control
API: Auto. Periodical Interrupt
VBG
API
LVR
PIN
LVR
API
LVI
POR
Freescale Semiconductor
V
V
V
POR
V
DDPLL
SSPLL
DD
SS

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