CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 855

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

22.3.2.40 Port P Data Direction Register (DDRP)

Read: Anytime.

Write: Anytime.

This register configures each port P pin as either input or output.

If the associated PWM channel or SPI module is enabled this register has no effect on the pins.

The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0

channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for

If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.

Freescale Semiconductor

Data Direction Port P

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTP or PTIP registers, when changing the DDRP register.

Figure 22-42. Port P Data Direction Register (DDRP)

Table 22-39. DDRP Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)