CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1033

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
24.0.9.2
No low-power options exist for this module in wait mode.
24.0.9.3
All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H,
and J.
Initialization and Application Information
It is not recommended to write PORTx and DDRx in a word access. When changing the
register pins from inputs to outputs, the data may have extra transitions during the write
access. Initialize the port data register before enabling the outputs.
Power consumption will increase the more the voltages on general purpose input pins
deviate from the supply voltages towards mid-range because the digital input buffers
operate in the linear region.
Wait Mode
Stop Mode

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