CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 144

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
144
CC[3:0}
FIFOR
Field
3:0
4
FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e., the old data has been lost). This flag is cleared when one of the following occurs:
0 No over run has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag remained set)
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0,
CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6.
If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the
conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion
counters wraps around when its maximum value is reached.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the
conversion counter even if FIFO=1.
• Write “1” to FIFOR
• Start a new conversion sequence (write to ATDCTL5 or external trigger)
Table 4-18. ATDSTAT0 Field Descriptions (continued)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Freescale Semiconductor