CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 576

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 15 Background Debug Module (S12XBDMV2)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte

of the condition code register of the user’s program. It is also used for temporary storage in the standard

BDM ﬁrmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.

Special Single-Chip Mode

All Other Modes

BDM CCR LOW Holding Register (BDMCCRL)

When BDM is made active, the CPU stores the content of its CCR

in the BDMCCRL register. However, out of special single-chip reset, the

BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the

BDMCCRL register is read zero.

Bus clock dependent on oscillator

Alternate clock (refer to the device speciﬁcation to determine the alternate clock source)

Bus clock dependent on the PLL

Figure 15-4. BDM CCR LOW Holding Register (BDMCCRL)

MC9S12XDP512 Data Sheet, Rev. 2.21

Table 15-3. BDM Clock Sources

Freescale Semiconductor