CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1020

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.53 Port J Reduced Drive Register (RDRJ)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
24.0.5.54 Port J Pull Device Enable Register (PERJ)
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up
device is enabled.
1022
RDRJ[7:6]
RDRJ[1:0]
Reset
Reset
Field
7–0
W
W
R
R
RDRJ7
PERJ7
Reduced Drive Port J
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
0
1
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
RDRJ6
PERJ6
Figure 24-56. Port J Pull Device Enable Register (PERJ)
0
1
6
6
Figure 24-55. Port J Reduced Drive Register (RDRJ)
Table 24-49. RDRJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
0
0
0
0
4
4
Description
0
0
0
0
3
3
0
0
0
0
2
2
RDRJ1
Freescale Semiconductor
PERJ1
0
1
1
1
RDRJ0
PERJ0
0
1
0
0