CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 779

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.5.4
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module
or the S12XCPU provided the S12XDBG module is not armed, is configured for tracing (at least one
TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is
locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write
to DBGTB when the module is disarmed. Multiple writes to the DBGTB are not allowed since they
increment the pointer.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
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COCF
XOCF
XACK
Field
CRW
XRW
XSZ
5
4
3
2
1
0
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing S12XCPU activity in Detail Mode.
0 Write Access
1 Read Access
S12XCPU Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit
only contains valid information when tracing the S12XCPU accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains
valid information when tracing XGATE activity in Detail Mode.
0 Word Access
1 Byte Access
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing XGATE activity in Detail Mode.
0 Write Access
1 Read Access
XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle.This bit only contains valid information when tracing the S12XCPU accesses in Detail Mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
Reading Data from Trace Buffer
Table 20-42. CXINF Field Descriptions (continued)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Chapter 20 S12X Debug (S12XDBGV3) Module
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