CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 443

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

10.3.2.18 MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)

The identiﬁer mask register speciﬁes which of the corresponding bits in the identiﬁer acceptance register

are relevant for acceptance ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to

program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”

To receive standard identiﬁers in 16 bit ﬁlter mode, it is required to program the last three bits (AM[2:0])

in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”

Freescale Semiconductor

Module Base + 0x0014 (CANIDMR0)

Figure 10-22. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3

Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

0x0015 (CANIDMR1)

0x0016 (CANIDMR2)

0x0017 (CANIDMR3)

Table 10-21. CANIDAR4–CANIDAR7 Register Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)