CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 670

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 18 Memory Mapping Control (S12XMMCV3)
18.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU)
Read: Anytime
Write: Anytime when RWPE = 0
670
Address: 0x011F
SHU[6:0]
Reset
Field
6–0
W
R
RAM Shared Region Upper Boundary Bits 6–0 — These bits define the upper boundary of the shared
memory in multiples of 256 bytes. The block selected by this register is included in the region. See
for details.
1
1
7
Figure 18-20. RAM Shared Region Upper Boundary Register (RAMSHU)
= Unimplemented or Reserved
SHU6
1
6
Table 18-18. RAMSHU Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
SHU5
1
5
SHU4
1
4
Description
SHU3
1
3
SHU2
1
2
Freescale Semiconductor
SHU1
1
1
Figure 18-25
SHU0
1
0

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