CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 517
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.2
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
12.2.1
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
12.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
Freescale Semiconductor
Bus Clock
Interrupt
Request
SPI
External Signal Description
MOSI — Master Out/Slave In Pin
MISO — Master In/Slave Out Pin
SPPR
SPI
SPI Baud Rate Register
Prescaler
SPI Control Register 1
SPI Control Register 2
Baud Rate Generator
SPI Status Register
SPI Data Register
Interrupt Control
SPIF
3
SPR
MODF
Clock Select
Counter
SPTEF
3
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 12-1. SPI Block Diagram
Baud Rate
LSBFE=1
LSBFE=0
8
8
Control
Control
Master
Slave
Master Baud Rate
Slave Baud Rate
MSB
2
2
Shifter
LSBFE=1
LSBFE=0
LSBFE=0
LSBFE=1
CPOL
Clock
Shift
Phase +
Polarity
Control
Phase +
Polarity
Control
Chapter 12 Serial Peripheral Interface (S12SPIV4)
LSB
CPHA
BIDIROE
SPC0
Sample
Clock
Data Out
SCK In
SCK Out
Data In
Control
Logic
Port
MOSI
SCK
SS
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