CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 444
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
444
Module Base + 0x001C (CANIDMR4)
AM[7:0]
Field
7:0
Reset
Reset
Reset
Reset
Figure 10-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
W
W
W
W
R
R
R
R
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
0x001D (CANIDMR5)
0x001E (CANIDMR6)
0x001F (CANIDMR7)
AM7
AM7
AM7
AM7
0
0
0
0
7
7
7
7
Table 10-22. CANIDMR0–CANIDMR3 Register Field Descriptions
AM6
AM6
AM6
AM6
0
0
0
0
6
6
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
AM5
AM5
AM5
AM5
0
0
0
0
5
5
5
5
AM4
AM4
AM4
AM4
Description
0
0
0
0
4
4
4
4
AM3
AM3
AM3
AM3
0
0
0
0
3
3
3
3
AM2
AM2
AM2
AM2
0
0
0
0
2
2
2
2
Freescale Semiconductor
AM1
AM1
AM1
AM1
1
0
1
0
1
0
1
0
AM0
AM0
AM0
AM0
0
0
0
0
0
0
0
0
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