CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1239
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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A.1.5
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
1
2
3
4
5
A.1.6
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
Freescale Semiconductor
Num
Beyond absolute maximum ratings device might be damaged.
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute
maximum ratings apply when the device is powered from an external source.
All digital I/O pins are internally clamped to V
Those pins are internally clamped to V
This pin is clamped low to V
10
11
12
13
1
2
3
4
5
6
7
8
9
I/O, regulator and analog supply voltage
Digital logic supply voltage
PLL supply voltage
Voltage difference V
Voltage difference V
Digital I/O input voltage
Analog reference
XFC, EXTAL, XTAL inputs
TEST input
Instantaneous maximum current
Instantaneous maximum current
Instantaneous maximum current
Storage temperature range
Single pin limit for all digital I/O pins
Single pin limit for XFC, EXTAL, XTAL
Single pin limit for TEST
Absolute Maximum Ratings
ESD Protection and Latch-up Immunity
2
DDX
SSX
SSPLL
to V
to V
, but not clamped high. This pin must be tied low in applications.
2
5
SSR
DDR
Rating
Table A-1. Absolute Maximum Ratings
SSPLL
and V
and V
MC9S12XDP512 Data Sheet, Rev. 2.21
and V
SSX
SSA
3
DDA
4
and V
DDPLL
DDX
.
, V
SSR
and V
DDR
SS35
V
or V
Symbol
V
V
V
RH,
DDPLL
T stg
V
V
VDDX
VSSX
DD35
V
TEST
I
I
I
DL
DT
DD
ILV
D
IN
SSA
V
or V
1
RL
and V
DD35
Appendix A Electrical Characteristics
DDA
–0.25
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Min
–25
–25
–65
).
.
Max
10.0
+25
+25
155
6.0
3.0
3.0
0.3
0.3
6.0
6.0
3.0
0
Unit
mA
mA
mA
V
V
V
V
V
V
V
V
V
1241
C
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