CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 218

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 XGATE (S12XGATEV2)
ADDH
Operation
RD + IMM8:$00
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition
and stores the result in the high byte of the destination register RD. This instruction can be used after an
ADDL for a 16 bit immediate addition.
Example:
CCR Effects
Code and CPU Cycles
218
N:
Z:
V:
C:
ADDH RD, #IMM8
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]
Z
ADDL
ADDH
V
Source Form
old
old
& IMM8[7] & RD[15]
& IMM8[7] | RD[15]
C
R2,#LOWBYTE
R2,#HIGHBYTE
RD
old
new
& RD[15]
Add Immediate 8 bit Constant
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
| RD[15]
Mode
IMM8
; R2 = R2 + 16 bit immediate
new
old
(High Byte)
1
& IMM8[7] & RD[15]
| IMM8[7] & RD[15]
1
1
0
1
Machine Code
RD
new
new
IMM8
ADDH
Freescale Semiconductor
Cycles
P