CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 725

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.5.3.2
The data stored in the trace buffer can be read using either the background debug module (BDM) module
or the CPU provided the DBG module is not armed, is configured for tracing (at least one TSOURCE bit
is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when
the module is disarmed. Multiple writes to the DBGTB are not allowed since they increment the pointer.
The trace buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1
and 0 of
Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the
RAM pointer will occur. Reading the trace buffer is not possible if both TSOURCE bits are cleared.
Freescale Semiconductor
XOCF
Field
XRW
1
0
Table
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing XGATE activity in detail mode.
0 Read/Write Access
1 Access
XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle.This bit only contains valid information when tracing the CPU accesses in detail mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
19-39. The bytes containing invalid information (shaded in
Reading Data from Trace Buffer
Table 19-42. CXINF Field Descriptions (continued)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Chapter 19 S12X Debug (S12XDBGV2) Module
Table
19-39) are also read out.
727