CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 132

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.3
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
132
1
ETRIGSEL
Only if ETRIG[3:0] input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source remains on one of the AD channels selected by ETRIGCH[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
ATD Control Register 2 (ATDCTL2)
ETRIGCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
Table 4-5. External Trigger Channel Select Coding
ETRIGCH2
MC9S12XDP512 Data Sheet, Rev. 2.21
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
ETRIGCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
ETRIGCH0
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
External Trigger Source
Reserved
Reserved
ETRIG0
ETRIG1
ETRIG2
ETRIG3
AN10
AN11
AN12
AN13
AN14
AN15
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
Freescale Semiconductor
1
1
1
1

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