CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 539

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4.7.4
The reset values of registers and signals are described in
Definition”, which details the registers and their bit fields.
12.4.7.5
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is
a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
12.4.7.5.1
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see
changed:
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in
12.4.7.5.2
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does
not clear until it is serviced. SPIF has an automatic clearing process, which is described in
Section 12.3.2.4, “SPI Status Register
12.4.7.5.3
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process, which is described in
Status Register
Freescale Semiconductor
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If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the byte last received from the master before the reset.
Reading from the SPIDR after reset will always read a byte of zeros.
MSTR = 0, The master bit in SPICR1 resets.
Reset
Interrupts
MODF
SPIF
SPTEF
(SPISR)”.
Table
12-2). After MODF is set, the current transfer is aborted and the following bit is
Section 12.3.2.4, “SPI Status Register
MC9S12XDP512 Data Sheet, Rev. 2.21
(SPISR)”.
Section 12.3, “Memory Map and Register
Chapter 12 Serial Peripheral Interface (S12SPIV4)
(SPISR)”.
Section 12.3.2.4, “SPI
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