CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 872

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0)

Read: Anytime.

Write: Anytime.

This register configures pins PAD[07:00] as either input or output.

DDR1AD0[7:0]

Data Direction Port AD0 Register 1

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is

Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to

read on PTAD01 register, when changing the DDR1AD0 register.

be set to logic level “1”.

Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0)

Table 22-58. DDR1AD0 Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor