CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 883

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.4.2.6
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose
I/O, or with the channels of the enhanced capture timer.
22.4.2.7
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-
purpose I/O, or with the SCI and SPI subsystems.
The SPI0 pins can be re-routed. Refer to
22.4.2.8
This port is associated with the SCI3, CAN4–0 and SPI0. Port M pins PM[7:0] can be used for either
general purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to
(MODRR)”.
22.4.2.9
This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either general
purpose I/O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1 and SPI2 modules. If the PWM is enabled
the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. If
SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined by status
bits in the SPI modules.
The SPI1 and SPI2 pins can be re-routed. Refer to
(MODRR)”.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion
Interrupts”).
Freescale Semiconductor
Port T
Port S
Port M
Port P
PS[7:4] are not available in 80-pin packages.
PM[7:6] are not available in 80-pin packages.
PP[6] is not available in 80-pin packages.
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 22.3.2.37, “Module Routing Register
NOTE
NOTE
NOTE
Section 22.3.2.37, “Module Routing Register
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Section 22.3.2.37, “Module Routing Register
(Section 22.4.3, “Pin
(MODRR)”.
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