CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 152

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.16.2
4.4
The ATD10B16C is structured in an analog and a digital sub-block.
4.4.1
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
4.4.1.1
The sample and hold (S/H) machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue
drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks
and the analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V
152
R (10-BIT)
R (10-BIT)
R (8-BIT)
R (8-BIT)
Reset
Reset
W
Figure 4-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
W
Figure 4-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
Functional Description
Analog Sub-block
BIT 7 MSB
Sample and Hold Machine
Right Justified Result Data
BIT 7
0
0
0
0
7
7
DDA
and V
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 6
BIT 6
SSA
0
0
0
0
6
6
allow to isolate noise of other MCU circuitry from the analog sub-block.
MC9S12XDP512 Data Sheet, Rev. 2.21
BIT 5
BIT 5
0
0
0
0
5
5
BIT 4
BIT 4
0
0
0
0
4
4
BIT 3
BIT 3
3
0
0
0
3
0
BIT 2
BIT 2
0
0
0
0
2
2
SSA
BIT 9 MSB
Freescale Semiconductor
BIT 1
BIT 1
to VDDA.
0
0
0
1
1
BIT 8
BIT 0
BIT 0
0
0
0
0
0