CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 76

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XD-Family
1.6.2
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states.
1.6.2.1
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
1.6.2.2
The RAM array is not initialized out of reset.
1.7
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See
Table 1-13
at global address $7FFF0E during the reset sequence
76
COP Configuration
and
Effects of Reset
I/O Pins
Memory
If the MCU is secured the COP timeout rate is always set to the longest
period (CR[2:0] = 111) after COP reset.
Table 1-14
for coding. The FCTL register is loaded from the Flash configuration field byte
FCTL Register
FCTL Register
NV[2:0] in
Table 1-13. Initial COP Rate Configuration
NV[3] in
Table 1-14. Initial WCOP Configuration
000
001
010
011
100
101
110
111
1
0
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
COPCTL Register
COPCTL Register
CR[2:0] in
WCOP in
111
110
101
100
011
010
001
000
0
1
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