CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 471

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode
is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ,
CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the
configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR,
CANIDMR message filters. See
detailed description of the initialization mode.
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 10-47., “Initialization Request/Acknowledge
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
10.4.5.6
The MSCAN is in power down mode
Freescale Semiconductor
•
CPU is in stop mode
MSCAN Power Down Mode
The user is responsible for ensuring that the MSCAN is not active when
initialization mode is entered. The recommended procedure is to bring the
MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the
INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going
message can cause an error condition and can impact other CAN bus
devices.
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
Bus Clock Domain
CPU
Init Request
INITAK
Flag
Figure 10-47. Initialization Request/Acknowledge Cycle
Section 10.3.2.1, “MSCAN Control Register 0
INITRQ
sync.
INITAK
MC9S12XDP512 Data Sheet, Rev. 2.21
(Table
10-36) when
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
NOTE
NOTE
SYNC
SYNC
Cycle”).
CAN Clock Domain
sync.
INITRQ
INITAK
(CANCTL0),” for a
INIT
Flag
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