CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 171

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.5
This register selects the conversion clock frequency, the length of the second phase of the sample time and
the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
SMP[1:0]
PRS[4:0]
Reset
SRES8
Field
6–5
4–0
W
7
R
SRES8
ATD Control Register 4 (ATDCTL4)
0
7
A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The
A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
0 10-bit resolution
Sample Time Select — These two bits select the length of the second phase of the sample time in units of
ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler
value (bits PRS4–0). The sample time consists of two phases. The first phase is two ATD conversion clock
cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node.
The second phase attaches the external analog signal directly to the storage node for final charging and high
accuracy.
ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
frequency is calculated as follows:
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler
ATDclock
8-bit resolution
value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.
Table 5-12
SMP1
Table 5-11
0
0
1
1
SMP1
=
-------------------------------- -
0
6
BusClock
PRS
illustrates the divide-by operation and the appropriate range of the bus clock.
Figure 5-7. ATD Control Register 4 (ATDCTL4)
+
lists the lengths available for the second sample phase.
1
Table 5-10. ATDCTL4 Field Descriptions
SMP0
MC9S12XDP512 Data Sheet, Rev. 2.21
SMP0
0.5
Table 5-11. Sample Time Select
0
1
0
1
0
5
PRS4
0
4
Length of 2nd Phase of Sample Time
16 A/D conversion clock periods
Description
2 A/D conversion clock periods
4 A/D conversion clock periods
8 A/D conversion clock periods
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
PRS3
0
3
PRS2
1
2
PRS1
0
1
PRS0
1
0
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